With an analog front end circuit which is used when the image signal is taken out from a charge coupled device serving as image pickup means in an electronic camera apparatus such as an electronic still camera or a video camera, a plurality of gain control methods such as those shown in FIGS. 3A to 3C have hitherto been performed.
FIG. 3A is a block diagram of an analog amplifier type analog front end circuit which performs a first method. In this circuit of FIG. 3A, an image analog signal which is produced by, for example, a charge coupled device (hereinafter abbreviated as “CCD”: not shown) is supplied to a correlated double sampling circuit (hereinafter abbreviated as “CDS”) 31 through an input terminal 30. The image analog signal is taken out through the CDS 31.
The signal which is taken out through the CDS 31 is supplied to an analog type programmable gain-control amplifier (hereinafter abbreviated as “the PGA”) 32. To this analog PGA 32 is further supplied a gain control signal from a control circuit 33. The signal which is amplified according to the gain control signal is supplied to an analog digital converter (hereinafter abbreviated as “ADC”) 34, and the converted digital signal is taken out from an output terminal 35.
In other words, this circuit of FIG. 3A is such that the analog PGA 32 performs the entire gain control as required. In order that this circuit provides a sufficient image quality for consumer use, the word length required for the ADC 34 is about 10 to 12 bits, so that a short word length is available for the ADC 34. Therefore, the circuit of low price can generally be used for the ADC 34a, and the less power consumption will also be achieved. Furthermore, the equivalent word length at the output end always corresponds with the word length of the ADC 34, and the noise level at the time of high gain is the lowest.
However, when the analog PGA 32 in the circuit, controls the entire gain range as required, the power consumption by the analog PGA 32 increases and hence the power consumption in the entire circuit also increases. Moreover, the analog PGA 32 is difficult to make linear of its gain control characteristic. Therefore, in order to obtain the linear characteristic, it becomes necessary to provide a conversion table, etc. on the relevant control software. As described above, the circuit of FIG. 3A involves such problems as the power consumption and the linearity of gain control.
In contrast, FIG. 3B is a block diagram of a digital amplifier type analog front end circuit which uses a second method. It is noted that, in that figure, the elements corresponding to those of FIG. 3A are denoted by like reference symbols. In this circuit of FIG. 3B, the signal which is taken out through the CDS 31 is supplied directly to the ADC 36. Then, the digital signal thus converted is multiplied by a gain control signal from the control circuit 33, which is performed by a digital type programmable gain control amplifier (PGA) 37.
Accordingly, in this circuit of FIG. 3B, the entire gain control as required is performed by the digital PGA 37. Because this circuit employs no analog PGA, the circuit structure is simple. In addition, there are less problems caused by the dispersion of circuits such as the offset, so that the operation becomes stable. Further, it is possible to make linear of the gain control characteristic of the digital PGA 37. As a result, providing the conversion table, etc. on the control software for obtaining the linearity can be made unnecessary.
However, in this circuit, the equivalent word length at the output end, etc. becomes smaller in inverse proportion to the gain which is the multiplication in the digital PGA 37. For this reason, in order to ensure the equivalent word length the maximum gain, it is necessary to make the word length of the ADC 36 long. Incidentally, the word length which is necessary for the ADC 36 to obtain a sufficient image quality for consumer use is about 14 bits. Accordingly, the ADC 36 having such a long word length will be large in circuit scale and also the power consumption thereof increases extremely.
Further, in the structure, for example, which omits a pre-amplifier for matching the output of the CCD with the input full scale of the ADC 36, in order to avoid the increase in the power consumption, if the maximum output level of the CCD in use is low, it will result that not all the input range of the ADC 36 are used. Therefore, the equivalent word length at the output end, etc. is reduced, which will result in a disadvantage in terms of image quality moreover, at the time of high gain, because all noises in the circuits that precede the digital PGA 37 are amplified, noises at high gain are disadvantageous.
FIG. 3C is a block diagram of a hybrid amplifier type analog front end circuit in which the analog and digital PGAs are mixed together to perform a third method. In this figure, the elements corresponding to those of FIG. 3A are denoted by like reference symbols. In this circuit of FIG. 3C, the signal which is taken out through the CDS 31 is supplied to the ADC 39 through an analog PGA 38, and the converted digital signal is supplied to the digital PGA 40. The gain control in these PGAs 38 and 40 are performed by the control circuit 33.
Accordingly, in this circuit of FIG. 3C, because the amplification is also performed by the digital PGA 40 as well, the gain of the analog PGA 38 can be made smaller than in the case of the circuit of FIG. 3A and thus the power consumption can be reduced. Also, because the amplification is performed in the analog PGA 38, the word length of the ADC 39 can be made shorter than in the case of the circuit of FIG. 3B. Note that the word length necessary for the ADC 39 in order to obtain a sufficient image quality for consumer use is about 12 bits. Therefore, the circuit which is cheap and of less power consumption can be employed for the ADC 39.
However, although this circuit of FIG. 3C is superior to the circuit of FIG. 3B in the noise at high gain but inferior to the circuit of FIG. 3A. The entire power consumption of the circuit of FIG. 3C is larger than that in the case where for example, the word length of the ADC 36 is made to be 12 bits in the circuit of FIG. 3B. In addition, problems of the instability of operation and the like due to interposing the analog PGA 38 still remain to exist as in the circuit of FIG. 3A. On the other hand, for example, in an electronic camera apparatus, there are cases where the increase in noise and the increase in the power consumption may be permitted depending on the use conditions.